Design Of High PSRR LDO Linear Regulator Based On 65nm SOI Process

Since entering the new century,China’s science and technology industry has developed rapidly.Various electronic products,wearable devices,and portable devices have emerged in an endless stream,and their functions have become more and more abundant.In addition,in recent years,the development of new energy vehicles have put forward higher requirements for power supply.As the most widely used chip,Low Dropout Linear Regulator（LDO）has incomparable advantages over other power management modules.However,previous LDO relied on large off-chip capacitors to ensure its own stability.Therefore,in order to cope with the widening of the signal processing frequency and the new requirements of ensuring the performance of the power supply,the research on high-performance LDO has become a trend and has broad market prospects.In order to design a high-efficiency LDO with lower noise,higher power supply rejection ratio（PSRR）,and faster response,this paper designs a high PSRR LDO based on 65nm SOI process.This LDO includes enable module,pre-regulator module composed of bandgap reference source and error amplifier,fast-start and filter module,clock module,power transistor and feedback loop.The performance of the BGR is improved by adding a PSRR enhancement circuit and a start-up circuit.The EA adopts a two-stage Miller-compensated operational transconductance amplifier as the main structure.The power transistor selects a large-sized PMOS to form a common source amplifier.The filter uses MOSFET is combined with a 1n A current source to form an RC filter to achieve low noise.At the same time,a switch MOSFET controlled by a clock signal is added to short-circuit the filter during the power-on phase of the circuit enable signal to achieve rapid startup of the circuit.The paper presents circuit design and analysis,pre-simulation results,layout design and optimization,and post-layout simulation results.The post-layout simulation results show that:in the full temperature range（-40～110℃）,when the power supply voltage is 4～5.5V,the output voltage is 2.6V,the quiescent current is1.2m A,the total current when VEN off is 2.83μA,and the output voltage tolerance is 0.13%,the temperature coefficient is 19.63ppm/℃,the PSRR is 67.2dB@1k Hz,67.4dB@10k Hz,56.3dB@100k Hz,the noise in the range of 10～100k Hz is 18.35μV_rms,and the startup time is620.8ns.The LDO circuit designed in this paper can provide a stable output voltage,which can be used to provide power supply voltage for different modules such as power amplifiers.For different voltage requirements,it can be adjusted by changing the ratio of the feedback resistor,and finally multi-scenario applications can be realized.