Research And Design Of A High PSRR Capacitor-Free Linear Regulator

With the continued popularity of portable electronic devices and more and more intelligent functions,the demand and performance of the market for power management chips are constantly rising.LDO are favored by the So C system due to their outstanding advantages such as simple structure,low noise,small PCB area.However,the noise effects of power supply and the crosstalk between digital-analog hybrid circuits become more and more serious with the development of So C.In addition,because of the increase in the number of load gates,the load capacitance at the output of the LDO can reach up to the order of n F.The increase in the number of load gates also means that more load currents are required.Therefore,the capacitance-free LDOs with high PSRR and large load characteristics become current trends in linear regulators.In this thesis,a high-PSRR capacitor-free LDO linear regulator is designed by studying the architecture and design concept of the capacitor-free linear regulator and combining the research difficulties of today's LDO.By setting the circuit parameters reasonably,only one main pole exists in the unity gain bandwidth so as to become a single-pole system and ensure the stability of the LDO loop in the output capacitance range of 0 to1?F.In order to get the best PSRR DC characteristics,the first stage of the LDO uses the cascode NMOS differential input amplifier,and the second stage uses the PMOS input common-source amplifier.Using a variable gain buffer consisting of two-stage common-source amplifiers improves the slew rate of the LDO and the stability during load transient transitions.For transient response characteristics of the LDO without off-chip capacitors,this thesis proposes a transient enhancement circuit that automatically detects output voltage to quickly sense the change of LDO load current,which greatly reduces the overshoot voltage and recovery time.At the same time,in order to reduce the drift of the bandgap reference voltage and improve the precision of the LDO circuit,a high PSRR bandgap reference circuit with negative feedback pre-regulation function is designed.Based on the TSMC 0.25-?m BCD process and simulated by the Cadence Spectre simulator,the simulation results show that the dropout voltage is 150 m V.The LDO is stable in the output capacitance range of 0 to1?F within the load current range of 1mA to 200 m A.When the load current is 200 m A,the maximum phase margin of the loop is 86° and the minimum phase margin can reach as high as 75°.The low-frequency PSRR can reach-80 d B and the 100 k Hz PSRR also has about-40 d B.Finally,except for the bandgap reference circuit,the quiescent current is 114?A at a load current of 1mA.