Research And Design Of Virtual Logic Analyzer Based On FPGA

With technology of digital, large scale integrated circuit and computer technology are popularizing and developing, logic analyzer is the mostly used universal and representative testing instrument in the domain of data testing. It makes great help for solving the problems of detecting and failures diagnose in more and more complicated digital system virtually. Virtual Instrument is the result of banding the technology of modern computer hardware and communication direction in the domain of measure instrument, which represents the current development direction in the domain of measure instrument. Now, with plentiful interconnection resources and high cost-effective, Field Programmable Gates (FPGA) is used widely in high-speed data acquisition. On the basis of above mentioned, this thesis discusses the research and design of virtual logic analyzer based on the full use of FPGA technology and virtual instrument technology.After the working principle and requirement analysis being surveyed, the system framework of Logic Analyzer is presented. The instrument is made up of two parts: application software on personal computer and the data-sampling system based on hardware circuit board. And the design of various component modules has been studied, including probe module, clock module, delay and latch module, spikes detection module, trigger identification module, storage and control module, USB interface module. In the specific design, this project mainly uses FPGA technology and some related knowledge with software and hardware. The completed system designs include acquisition module, trigger module, memory module, control module and interface module. These modules designed by Verilog HDL hardware description language combined with schematics in FPGA are core components of logic analyzer. And the thesis achieves trigger-generating circuit, trigger- selection circuit, trigger-release-suppression circuit, pre-trigger circuit, time-base circuit, front / rear-counting circuit, FIFO-memory-control circuit and communication-interface circuit. After the completion of the circuit design, the full FPGA circuit is simulated in function and timing on Quartusâ…¡of ALTERA Corp. And then debug the circuits on the GX-SOPC-EDA-STARTER-EDK development board to ensure the correctness and dependability of circuit. The system using programmable logic devices not only improves the system's integration, but also meets the basic functional requirements of logic analyzer. At the same time, during the debugging process the design can be revised several times to improve flexibility and reduce the cost.At the end of the thesis, a summary is presented and features and deficiencies of logic analyzer are introduced. At the same time, some suggestions are forward to improve the instrument, as well as the developing trend of logic analyzer in future.