The Deveioping Of New Miniature Display Terminal Of Airborne Radar

This thesis mainly deals with the updating and alteration of the display terminal of airborne radar of some model with the emphasis on the utilization of DSP and FPGA in radar display system. Using 8 bits micro-controller makes the old type many disadvantages, such as slow speed, simple function and so on. To get over it radically, the author puts forward the plan to import powerful DSP into the field of the airborne radar displaying termination for the first time. In addition, when designing the signal detection circuit, the author uses VLSI FPGA to plan ASIC which improves the system reliability, aggregation, maintainability and the signal process speed and reduces the display volume greatly. The main functions of the system are as follow: Firstly the whole system is controlled by TMS32OC5O and GAL. Secondly the generation of displaying scheduling, the control of the video memory, the sliding window accumulation and the threshold detection of target echo signal are realized by means of FPGA. Furthermore, with it a UART is extended. Finally the first and second photo are transferred into video signal accordingly which are transmitted to the displaying screen.