Research On Methodology Of SoC System Level Verification Based On Random Testing

According to Moore's Law, the number of transistors per chip doubles every 18 to 24 months. The escalation in gate count has enabled the electronics industry to make major strides in producing smaller and faster consumer and communication products. The development of microelectronics makes these products contain multiple functions on a single IC (Integrated circuit), supported by various custom-designed and third-party Intellectual Property (IP). These single chip systems are called SoC (System-on-Chip).Although the advance from ASIC (Application Specific Integrated Circuit) to SoC can provide more and more functionality for a single chip, it presents enormous verification challenges for SoC designs. The traditional verification methods become less and less powerful as the scale and complexity increase. During RTL (Register Transfer Level) verification, the using of HDL (Hardware Description Language) software simulators has been proven to be inefficient and more time-consuming. In additional, these approaches lack the parallelism needed to rapidly verify the interaction between hardware and software blocks in a SoC design.In order to deal with the above limitations during the conventional verification, a new verification methodology for SoCs, methodology of SoC system level verification based on random testing, is proposed and established in the dissertation. On one hand, the new verification methodology is derived from the criteria: find more functional errors in the earlier SoC design cycles compared with register transfer level. On the other hand, the new verification methodology has deployed a feasible technique that can address the verification bottleneck for SoC design.The methodology of SoC system level verification and the theory of random testing are introduced directly at the start of this dissertation, which are the background for researches in the thesis. In fact, the new SoC verification methodology is brought forward based on knowledge in the above two aspects.Apart from the basic knowledge, the research of creating testbench for system level verification is on the basis of SystemC and SystemC Verification Standard (SCV). Specifically, testbench for system level verification according to the new methodology is described using SystemC 2.0. Moreover, test cases for the system level testbench is generated according to three different mechanisms of randomisation based on SystemC Verification Standard specification, which consist of direct randomisation, weighted randomisation and constrained randomisation typically used in verification.The new verification approach can be implemented on the platform of SoC system level verification, which is constructed by integrating compiling, linking and debugging tools and installing SystemC and SystemC Verification Standard libraries on a Sun Blade 2000 workstation. Actually the platform is a part of WHU SLD 1.0 that is the tool prototype for SoC system level design developed in a National 863 Project about researches on SoC hardware/software co-design and co-verification.The methodology of SoC system level verification based on random testing is demonstrated on a series of experiments, which implement functional verifications on system level models of 4 X 4 package switch. The thesis sets forth in detail how to create system level testbench for the verification, how to bind the testbench and theDesign Under Verification (DUV) and how to generate test stimuli in accordance with three types of randomization in SystemC Verification Standard. Through analysing results of four different experiments that verified different functions provided with the system level model of 4 X 4 package switch, the new verification method put forward in this dissertation has been evaluated contrarily. The results have indicated that the method proposed in the paper can be used to fulfill SoC system level verification efficiently.