The Research On Boundary Scan Test Of FPGAs

Field Programmable Gate Array (FPGA) is a new kind of device, what combines the structure in common use of gate array and the characteristics of field programmable together. Now, the FPGA serial devices are becoming one of the most popular devices. With the extensive application of FPGA, the function in the digital system is more important. So, the more overall research on the fault testing and diagnosing is significant. With the fast expand of the scale of the integrated circuit, the structure of the circuit becomes more complex, which make numbers of defaults is not easy to test. People turn sight to problem of design for testability. The proposition of the problem of design for testability offers a new effective way for solve the problem of testing, one of the important technology of which is boundary scan test(BST).This paper introduces the structure characteristic of FPGA, some basic concepts and theories of BST. The mathematics descriptions and mathematics models of BST utilizing the matrix theory are given. In this paper, the problem of test optimizing in the BST is mainly discussed, and the existing arithmetic which solves two kinds of optimization problems is provided. This paper analyzes their advantages and shortcomings, puts forward the improvement to two kinds of existing algorithms, compares the performance of optimization algorithm that before and after improving. Finally, this paper summarizes the concrete course of test FPGA utilizing BST.