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Design And Realization Of Multi-Service PDH Based On Single FPGA Chip

Posted on:2006-09-20Degree:MasterType:Thesis
Country:ChinaCandidate:Z S YangFull Text:PDF
GTID:2168360152470966Subject:Electronic Science and Technology
Abstract/Summary:PDF Full Text Request
With the development of communication network and the improvement of user's requirement, PDH is gradually replaced by SDH in optical fiber communication. SDH optical fiber communication system is being used widely by its advantages: huge volume of communication, high performance of transmission, facile configuring and powerful management. But in some case when huge volume of communication is not needed, the potential and advantages of SDH can't be exerted and most of volume is wasted. On the contrary, in some special case PDH have advantages for its moderate volume, facile configuring, low cost, high reliability and plentiful function.In this thesis, we design and realize a single chip FPGA transmitting system based on PDH technology for the requirement of practice. The system which is mainly designed on single FPGA chip could transmit 12 El signals and 1 100M Ethernet tunnel, and this solution have obvious advantages in integration, power, cost and flexibility.Firstly, we introduce digital communication and the principle of multiplexer as well as ethernet. Then we describe the solution of our transmitting system in detail, also we introduce the chip used in this system including the main FPGA chip. Finally, the circuit board is designed and the RTL coding is writed, then both hardware and verilog code debug is performed. The author's main tasks includes:1.Implement the multiplexer of 4 El signals, the main circuit includes all digital phase-locked loop(DPLL), HDB3 encode and decode, positive justification, the start of frame detect circuit, multiplex and demultiplex circuit.2.Map the Mil signals which come from 100M ethernet from 25M bit/s to 25.344M bit/s.3.Encode the El multiplexer signals and Mil signals with 5b6b encode-decode scheme, then transmit the 152.074M signal by optical fiber.4.Use the clock and data recovery solution of XILINX to recover the high-speed clock. And decode the signal with 5b6b, then demultiplex the El and ethernet signals.
Keywords/Search Tags:PDH, El, Multiplexer, Positive Justification, DPLL, M1I, CDR
PDF Full Text Request
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