The Research On Testable Design Of Programmable Logic Devices With AND-OR Arrays

With science and technology development and electronic technique applications, the research and development of electronic product have been promoted, and electronic design automation has been improved.So there appear Large Scale Integrated Circuits (LSICs) and Systems on Chip(SoC). Because the design cost of Application Specific Integrated Circuit(ASIC) is very high and the time of its design is very long, and yet Programmable Logic devices(PLDs) are designed easily, design time short, and they can be recycled. PLDs have been swiftly and violently developed. Their integrated scales have been enhanced, and they may be made into intellectual propertys (IP) of SoC. And then the product qualities cause more attention. How to examine the quality of PLDs and to make certain the quotiety of finished product have become urgent affairs, and have been established into two large research tasks in the electronic design with the circuit function design.Hard following science and technology development, the thesis focuses on the testable design of PLDs with AND-OR arrays. At first, the known testable design schemes of AND-OR arrays are studied and analysed, and four schemes of testable design have been gained, namely, the concurrent testable design of using special coding, the testable design of using parity checking, the testable design of signature analysis, and the divide-and-conquer testable design. At the same time the technique of boundary scan in PLDs is introduced too. Second, a new-style testable design scheme for AND-OR arrays is introduced based on output-inversion and portrait-observation. The scheme adopts a special disposal method by the structure characteristics of PLDs, which, in the test mode, may regard the original outputs as inputs, and compress the test results by jointing cascades of XOR gates at the portions of the product lines. The analysis of all test techniques and their application conditions results in the conclusion that the scheme does not only use a universal test set and decrease the number of test, but also abundantly reduce area overhead in ensuring high fault coverage, and especially fit for the built-in test design of very large scale PLDs. At last, the steering design schemes for the built-in self-test design of very large scale PLD are brought forward: testing AND-ORarrays by using the scheme based on output-inversion and portrait-observation; testing interior flip-flop by adopting the scan path technique. More over,the generation and infliction of the test pattern and the response of the test result with or without boundary scan circuits are discussed.The proposal of a new-style testable design scheme based on output-inversion and portrait-observation for AND-OR arrays and the discussion of the built-in self-test of very large scale PLDs provide tremendous motivation for the research, application and spread of PLDs. As a result,PLDs will be enhanced in the quantity and the quality.