A FPGA Implementation Of Turbo Decoder Based On Linear Prediction Control

Turbo code is the milestone in Err-correcting theory. Its good performance nearlyup to Shannon Capacity shows how important the SISO iterative decoding method is,which is based on interleave and de-interleave manner. As the iteration number in-creases, BER decreases nearly up to Shannon Capacity gradually. Turbo decoding isfeatured with complex decoding algorithm, great data save burden and long decodingdelay, which haltered its application. This paper is trying to implement Turbo decoderin a new perspective on FPGAs and it referred to numbers of articles beforehand. First,it introduces Turbo code theory, FPGA techniques and Linear Prediction Control theo-ry. And then, it presents module description in this design and detailed design methodused here. At last, it gives results.Turbo decoding typically accompanies large computation task and there existsnon-linear functions in decoding algorithm. To cope with this trouble, design adoptsMax-log-Map, sub-optimal alternative of Map, to be the decoding algorithm for eachconstituent decoders. Max-log-Map is the linear version of Map and it makes a com-promise between feasibility and performance. Considering decoding procedure is pro-cessed one by one and there is long logic chain in each procedure in case of complexalgorithm, a longer logic chain will be produced along all procedures. In order to geta short delay from register to register and then a higher fmax of circuit, design insertsseveral registers along combinational chain between registers using pipelining tech-nique. In order to reduce design area, received data, backward recursiveβin Max-log-Map and exterior information Le generated during iterations are backed up to SRAMconnected to FPGA through SRAM Controller. At the same time, a decoding mod-ule is multiplexed to constituent decoders. Whether a Turbo decoder can be used incommunication system is in correlation with its decoding delay. Design uses exteriorinformation Le from previous n iterations to predict Le of (n + 1)th iteration using Lin-ear Prediction Control algorithm and the predict value will be input to next (n + 2)th iteration. Delay generated during a iteration will be reduced. Timing design of onedecoding word is reported regarding its algorithmic operation and save process. 12system clocks are used to compute and saveβ, 14 system clocks to compute and saveLe and 8 system clocks to predict and save Le.