The Research On Optimizing The Test Time On Three-dimensional Integrated Circuits

With the rapid development and manufacturing process continuous improvement of integrated circuit technology, the number of IP cores on a chip is growing fast so that the interconnects are increasing sharply. The overlong interconnects impact on the performance of ICs seriously and hamper its further improvement. The appearance of 3D ICs solved the inherent bottlenecks of traditional circuit development thoroughly. 3D ICs adopt a method by multiple active device layers stacked together with direct vertical interconnects. The direct vertical interconnects are named Through Silicon Vias (TSVs). The length of wire has been shortened sharply because the original vertical attachment has replaced the edge wiring way in PCB. The transmission delay and transmission power consumption have been reduced. Package density has increased. Different type of chips can be packaged together. Even if a silicon layer is faulted we can repair it individually which can improves the system maintainability. Thus 3D ICs is a new trend of future development of the integrated circuit.Design methods, manufacturing methods and testing methods are the three components of IC development. The testing of ICs becomes more and more intractable since the evolution of integrated circuits has developed to the point where millions of transistors can be integrated on a single chip. In order to reduce the test difficulty and simplify the test method, many people put forward the ideas of design for test which can make the test methods be joined to the preliminary design. The ideas of design for test can reduced the cost of test significantly. For the problem of design for test in 3D ICs the main work of the thesis is as follows:1. Introduce the development trends, the generated technical background and the research developments of 3D integrated circuit. Analyse the testing wafer, testing TSVs and design for test of 3D ICs.2. A test solution for 3D Network-on-Chip (NoC) with test time optimization is presented. Use Coarse-granularity partitioning for IP cores. Firstly we select the appropriate IP cores for each layer according to the test time of unwrapped cores in order to balance the test time of IP cores on each layer. Secondly we use integer linear programming (ILP) and random rounding method to allocate TAM bit-width for each layer under the constraints of the total TAM bit-width. Then we can reduce the test time of IP cores on each layer further. Simulation results are presented that the test time for 3D NoC has been reduced significantly.3. A test method for 3D SoCs under pre-bond test pins and power consumption constraint is presented in this paper. Use fine-granularity partitioning for cores, the number of flip flops in each IP core are partitioned balanced into each layers and interconnected by TSV. A novel 3D IC core wrapper scan-chain is designed and a SoC test scheduling method is proposed under pre-bond test pins and power consumption. Experimental results demonstrate that the test time can be reduced sharply and need less power consumption .