Research And Implementation Of Multi-standard DCT Algorithm And It's VLSI Architecture

Discrete cosine transform DCT which is an orthogonal transformation is widely used in video and image processing technology, including the current mainstream image and video coding standards adopted the DCT transform, such as JPEG,MPEG-4,H.264,AVS,etc. The DCT algorithm structure for supporting a single standard is very mature at present. But there are few algorithms which support multiple, especially those support the above four standards.The main research content of this paper is stated as follows.Firstly, study the DCT algorithm and related scaling and quantization principle of the above four standards. After researching on the merit and demerit of several DCT algorithms, the reusable DCT VLSI architecture is researched from the aspect of chip area, speed, and precision, etc.In this paper, the 2×2 Hadamard, 4×4 Hadamard, 4×4 DCT, 8×8DCT H.264 inside of H.264 is reused, which saves the area. By introducing integer transform matrix, and increased scaling module, the reusable DCT architecture is designed for supporting JPEG, MPEG-4 and H.264.Through the Xvid MPEG-4 codec verification, accuracy meets the requirements. Two methods are proposed for scaling module, which are optimized from the aspect of area and frequency. The reusable and area efficient 8×8 DCT is designed for H.264 and AVS, through two kinds of architecture. The one is based on matrix decomposition method and the other is based on W.H.Chen architecture. So the 1-D 8×8DCT algorithm cost 42 adders for the former method, and 36 for the latter method. So the latter method is more economical than only realizing the algorithm in the AVS reference code.On the basis of the above design, the common DCT algorithm architecture is proposed, which supports the above four standards. The common first scaling module for JPEG, MPEG-4 and AVS is optimized by two methods. The first method is reusing 8 multipliers, the second is reusing 66 adders, and they both optimized the area and frequency. The second scaling and quantization module which is a common module for the four standards is designed by saving the area.Secondly, the multi-standard DCT is hardware implemented.It mainly contains control module, FDCT1/FDCT2 module, transposition module, first scaling module, zoom, second scaling quantization binding module. On the basis of in ensuring the throughput and speed, the pipeline depth and area is reduced for transposition module. For the multiplier method of the first scaling module and the second scaling quantization binding module, the area is reduced and frequency is increased by optimizing the complement multipliers.Finally, the PC simulation and FPGA Prototype Verification of the multi-standard DCT is completed. The PC automatic verification platform and FPGA automatic verification platform are implemented.