Research And Design Of Architecture And Central Control Module In Multi-standard Video Post Processing Chip

Multi-standard Video Post-processing Chips is designed for computers and high-definition display device. The main function is to complete the standard uniform and standard computer display timing and display timing between the HD conversions. The chip includes Analog Front End, central control module, scaling module, and face skin color enhancement. The multi-format video display processing chips can be used in a variety of environments, such as in a multimedia display device, LCD, digital high-definition television display, the Cathode Ray Tube (CRT) and projection equipment and plasma display equipment.This paper describes low-power chip architecture, pattern recognition module and pixel clock generation module modules of theory and design process and verify the results. AFE includs pattern recognition module and pixel clock generation module. Pattern recognition to identify the main functions of the input video signal format, but the input signal may be interference and noise problems about signal integrity, and metastable conditions may also occur. Pixel clock generation module main function is to generate the pixel clock frequency dynamically changes with the input video and user-configurable pixel clock phase, to require the input pixel clock and line sync signal phase relative alignment, that is, the user configuration phase overall, after the original pixel clock and phase remain constant. Control module is the core of chip, which used the method of low-power design, and controls analog video front-end, I2C slave device, scaling module, a lookup table module, the output timing control module and the color enhance the data exchange module problem, and to prevent bus conflicts it controls chip internal bus arbitration as arbiter. On-chip bus used to simplify the Wishbone protocol, in this design, because a lot of video data and high frequency clock cycle, Wishbone interface must be designed as fast as it can.This article first discusses the theoretical basis for the design of each module, and then used to top-down design method, each sub-module of the more specific structure and its design. According to the division of modules completed the preparation of RTL code, and finally achieved in FPGA development board.