Design Of Software And Hardware Co Simulation Platform Based On FPGA

With the development of integrated circuit fabrication technology, multi-processor architectures will become the mainstream. As multi-processor architectures include excessive units, speed of software simulation can hardly catch up increasing complexity of design, and FPGA simulation is restricted by its capacity. As a result, it is of great significance to study hardware-accelerated simulation for future chip multi-processor architecture, and to develop software and hardware co-simulation platform based on FPGA.Firstly, this thesis compares advantages and disadvantages of different solutions, and determines software and hardware co-simulation proposal based on FPGA acceleration and software simulator. This proposal accelerates simulation of design under test (DUT) by downloading the design to FPGA. With the help of Ethernet interface on FPGA board, FPGA communicates with host at high speed, and test stimulus, which are generated on host, are transmitted to the design. Second, based on the proposal above, this thesis designs the structure of co-simulation platform. The platform is divided into three main modules: Ethernet interface, co-simulation module (CSM), and DUT. Ethernet interface, which includes WISHBONE interface, send module, receive module, control module, MII module, status module, and registers module, is responsible for high-speed communication between FPGA and host. CSM, which consists of analyze module, send module, registers configuration, response module, and digital clock manager, is responsible for controlling test of DUT. Then, adopting top-down IC design flow, modules above are designed.At last, hardware acceleration unit, combined with modules above and DUT, is downloaded to FPGA, and communicates with software simulator on host at high speed. The whole system design has passed pre-layout simulation and post-layout simulation, and has been verified by running on real platform.