FPGA Implementation Method Of Lifting Wavelet

JPEG2000 is a new image compressing standard, which is founded to replace the existing standard JPEG step by step. To realize the tools which the standard defines, the instantaneity of realization of JPEG2000 compression system is considerably essential. Based on the thorough research on the hardware-realizing-arithmetic of various existing lifting-wavelet, this thesis executes some investigation and development on the FPGA implementation method of lifting-wavelet, and designs a practical lifting-wavelet system based on the Altera Cyclone FPGA chip.This thesis firstly analyzes and investigates the realization method of discrete wavelet transform and its corresponding lifting arithmetic. Afterward, software simulations are carried out on the same image. The amount of the operation between the lifting method and the classic convolution method is compared and analyzed.Secondly, the LS97 wavelet coefficients are inducted to design a hardware system with a lifting-wavelet scheme, which contains a module that is used to isolate the inside data of the system from the outside. The module can enable the clock of the inputted data independent of the system inner clock, as well as the image resolution to be restricted only by the size of FPGA on-chip RAM. The system also includes a wavelet calculating module and a buffering module which is designed to transpose the storage. These two modules enable the system to calculate directly during carrying out the wavelet-transform without buffering the whole frame of image. Thus the cost-time of the wavelet-transform is reduced.Finally, the calculating results of software simulation and hardware simulation are contrasted. The main reasons of error and the feasibility of correction are researched, and a resolving scheme is brought up. The running-speed and the occupied-resource are introduced as performance guidelines, and an advanced method is put out to promote the system performance.