8051 SOC Design Based On FPGA

This paper introduces the design of 8051 SOC(System On Chip ).The design is described by VHDL,and also implemented on Xilinx FPGA (XC3S400) .The design thinking and technique of SOC and integration of IP (Intellectual Property) are also discussed.In the paper, it firstly introduces the developing of the single chip and the programable device, also introduces the relation between single chip and programable device on designing SOC.In order to increase the function of the SOC, it designs some interfaces of 8051 's peripheries, including the drive interface of LCD display, the interface of key and digital LED with automatically scanning, one DAC (Digital to Analog Conversion) with 8 bits and one PWM (Pulse-Width Modulation) with 12 bits. Besides these, it implements the 64K×8bit ROM and 64K×8bit RAM of the 8051 in the FPGA. The 8051 SOC adopts soft 8051 IP as microprocessor .The IP is based on the Intel'51 for design. The design ameliorates the function of serial communication, from original single SBUF to 16 Bytes. It improves the performance of serial communication. And in order to add more serial communication, by modifying the parameter of the IP, the number of serial communication increases to 2 interfaces. It meets the need of application.In the 8051 SOC, each IP Core is connected by the on chip bus -Wishbone which isused with Share Bus mode. The 8051 SOC passes the simulation and synthesis with EDA tools, and at last it downloads the design into the Xilinx FPGA for verification .The result shows that the design is well running.This paper has contributed a lot to the design of the more complex SOC. Simultaneously it has given the way to the design of SOC based on IP Core. In the end of the paper, it summarizes the experience on the course of designing SOC.