Design And Implementation Of Cryptography RSA IP Core

Throughout the ages, there is a problem that has been studied for people toexplore security issues of confidentiality of information and communication.Wartime, whether ancient or modern communications confidential security are thekey factors of the war’s victory; peacetime especially prevalent in the explosion ofinformation and e-commerce today, the confidentiality and security of informationis more important.The work of this thesis originates from: horizontal subjects "the development ofsecurity chip in smart grid". It needs to design an encryption chip which couldeffectively preserve personal privacy information and important data for smart gridsecurity requirements. After the in-depth research and analysis of RSA, this thesisproposes an RSA IP which could support RSA-1024mode, be compatible withWishbone bus.This paper analyzes the RSA cryptosystem algorithm to select a suitable designin this article from the low to the high scanning modular exponentiation algorithmand the Montgomery modular multiplication algorithm. Improved Montgomeryalgorithm for modular multiplication modules used in the RSA algorithm.OriginalMontgomery algorithm critical path delay of the two n-bit adder, and every time themultiplication remainder operation takes n times repeated, the papers for the1024-bit RSA design, if the critical path delay as compared to the two1024adderdelay, and every time the multiplication the remainder operation requires up to1024repetitions. Two1024-bit adder is not only delayed the computation time alsooccupy a fairly large area, so this thesis introduced carry-save adder consisted of fulladders to reduce the original1024carry adder delay, every one addition only onefull adder delay. A lookup table was introduced in order to better minimize area thanthe original retention carry adder faster and more space-saving structure, improvedMontgomery algorithm implemented in hardware.Finally, joins the IP with the encryption SOC system by Wishbone bus, theOR1200CPU executes assembler language instructions to control the IP core towork, and given a FPGA verification on the FPGA development board based onXilinx Virtex-2XC2VP30, Results prove that this desgin is fully comply with thestandard RSA.