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Research On Boundary-scan Test Technique Of Electronic Function Module

Posted on:2009-01-07Degree:MasterType:Thesis
Country:ChinaCandidate:L B QiFull Text:PDF
GTID:2178360245486506Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
With the increasing of printed circuit board function and the structure complexity, traditional test methods have been quite difficult to meet the test needs. As a complete and standardized design-for-test method, boundary scan technology provides a new way to test functions of circuit board device and interconnection. As the widespread of the chip which with a boundary-scan technique structure, to develop a boundary-scan test system, which can enhance the testability, reduce the maintenance cost of the electronic equipment has important significance.In the practice application, the boundary scan test is carried on in serial mode, in which the test time is requested much longer, and the certain accuracy of fault location through testing must be achieved following the test results. Because of the high request for test time and ability of fault diagnostic, and traditional test generation algorithm has great limitations. It is a significant research for finding a more efficient test generation algorithm.The boundary scan technique is researched, the fault models in the process of boundary-scan is tested, and the fundamental theory in boundary-scan are summed up. The generation principle and the ability of fault diagnosis of some conventional algorithms are analyzed. Based on the principle, methods and fault models, a new algorithm, named Improved Equal Weight Algorithm, is proposed. The algorithm achieves a reasonable tradeoff between the fault resolution and the compact index. It is an excellent performance test generation algorithm, and can reduce Confounding-fault syndrome.A boundary-scan test software is designed, which can automatically generate test graphics. The network list file and BSDL file essentially needed when generating test patterns, are analyzed in detail. Finally, experiments are carried on to test chip interconnect and chain integrity of PCB board level by transmitting testing protocol signal through the PC parallel port. Test results show that the system can accurately detect the integrity and interconnection faults of circuit board. Fault positioning accuracy can achieve pin level and meet the design requirements. The software has high practical value in the digital circuit fault diagnosis.
Keywords/Search Tags:boundary-scan, fault diagnosis, test generation
PDF Full Text Request
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