The Parallel Hardware Architecture Of Gaussian Elimination In Reconfigurable Computing System

Reconfigurable computing has become an active field in recent years. While combining the advantages of product standardization and application specialization, it fills the gap between traditional ISA processor and specialization system. Comparing to software, reconfigurable computing provides higher performance and lower power utilization. Besides, its low cost and flexibility show more superiority than specialization system. The well-known Gaussian elimination is a widely-used algorithm, one of traditional methods for solving dense linear systems of equations (LSEs), widely used in research and projects.This work is one of cooperations between HEU and ICRC, in which we implemented highe effient hardware Gaussian Elimination, and designed a system model of reconfigurable computing to verify the theory of accelerating with hardware. This work focuses on the optimization of algorithm, designing and testing of parallel architecture, and system model implementing and verifying.Firstly, background knowledge about reconfigurable computing technology is briefly summraized, including system architecture, application fields, current research highlight. Secondly, the algorithm in two branches of Gaussian Elimination over GF(2) and 32-bit IEEE754 floating-point is analyzed deeply and The logic of the traditional algorithm is changed in order to make use of parallelism in hardware. Then, the parallel hardware architecture of two algorithms is designed with quantitative simulation with EDA tools. At last, a prototype model of the reconfigurable computing system based on PCI-E technology is customized as an I/O connection between host and FPGA as well as the implementaiton of algorithm and the result are presented.