The Design And Implementation Of The Highly Reliable R80515 Based On FPGA

Single Event Upset refers to the phenomena that one certain bit of the digital circuit memory element inverts because of interference, thus changes the content of memory element. At present it is the main reason causing processor failure. SEU dose not destroy any semi-conductor device, but it will cause data error or instruction executing error, and even has the system ruined. SEU is an important reason that reduces the processor running reliability. As the integration density of the VLSI is continuously improved, the invertion effect of SEU is becoming more and more obvious. How to improve the fault-tolerant ability of the processor is a research hotspot in the field of high reliability processor design.Triple Modular Redundancy and Error Detection And Correction are the important methods to reinforce a digital circuit. Control Flow Detect can find the program execution errors during running, thus improves reliability of processors. Field Programming Gate Arrays is playing an increasingly important role in modern digital circuit design. FPGA is used in a wide rang from the simple interface circuit to the complex FSM, and even in SoCs. FPGA is being applied more and more widely in various fields.Firstly, open source IP core R80515 is analyzed deeply in this thesis, and then SEU in digital circuit is investigated. Based on these the high reliability architecture against SEU is presented; the implementation of EDAC coder and decoder is optimized to reduce FPGA resource usage; the effect of different TMR granularity on circuit reliability is analyzed and the conclusion that fine granularity TMR has higher reliability is pointed out. Finally, the key parts of R80515 are implemented on FPGA and provide support to CFD. The experiment results show that this architecture reinforce the R80515 on FPGA well.