The Optimization Of The Fingerprint FPGA Coarse Matching Accelerator

This paper first makes some improvements to the FPGA core of fingerprint coarse matching card, eliminating some problems in the original design which may occur in some odd circumstances, and optimazing the timing of the original design. The paper did some timing-simulation to the revised core matching module first, then downloaded the new code to Altera's Stratix II FPGA, and observed the waveform using Quartus II's embedded logic analyzer, thus verified the new code work well.After the coarse matching, the core returns the ID of library fingerprints, which accord with the field fingerprint, to the computer. This paper puts forward a method which utilizes the former free space of the library fingerprint in the original design. This method has such advantages as keep the original timing and easy to deveop. In order to raise the system's performance, the matching result is temporily stored in a queue. When the queue is stuffed to a certain extant, an interrupt is sent to inform 9054 to read the matching result from the queue. In the debugging phase, the queue is fulfilled with on-chip RAM, however, it can also be an dedicated chip if necessary.In this issue, the FPGA has not enough memory to store one batch of library fingerprints sent from PCI 9054, so it's connected to 4 IDT's IDT71V SRAM chips as external memory. This paper makes an presentation about the reading and writing of SRAM.The PLX's 9054 is a bus bridge compatible with PCI version 2.2. In this issue, it is used to turn complicated PCI protecol into simpler local bus protecol. This way the design is easier. This paper makes an presentation about the design of the interface to 9054. The last part of the paper is about the design of the application in the computer and the joint test of the application, the driver and the accelerator. A summary and prospect of the issue is given at the end of the paper.