Research On The Integrated Circuit Testing Method Of MRAM

As the widespread use of electronic devices in the area of lives, military, telecommunications and so on, IC(Integrated Circuit) technology takes an unprecedented development. IC testing becomes vital in the process of IC manufacturing,because it can ensure the correctness during design and production, as well as the reliability of the product. With the advance of circuit design method and IC process technology, integrated circuit is facing a higher defect density. Testing costs account for a big proportion of the total costs. In order to reduce the total costs of the products, the costs of test must be reduced at first. Therefore, it is critical to improve the testing techniques of IC. MRAM is considered as the ideal memory of electronic equipments, which is a new magnetic random access memory and has lots of advanced features that traditional memories do not have. This thesis aims at studying an integrated circuit testing method which can be applied to MRAM and test the faults of MRAM. The main research achievements are summarized as follows:Firstly, the MRAM faults models are proposed according to the structural characteristics of MRAM. Based on the existing RP15N algorithm, the author has presented a new algorithm—RP17N algorithm. Furthermore, the RP17N algorithm has been extended to the word orientation MRAM, which is called RP17NW algorithm.Secondly, a new testing circuit structure of MRAM has been built by using of the Top-Down approach; the implementation circuit of each sub module is designed in detail.Thirdly, the functional simulation and logic synthesis of MRAM BIST circuit have been achieved respectively by ModelSim SE 6.2e and Synplify Pro 8.1. The timing simulation is accomplished by Xilinx ISE 8.1i. Simulation and synthesis results show that the proposed algorithm and IC testing circuit can not only meet the demands of IC fault testing, but also accomplish a better compromise of area, power consumption and rate.