Receiver Design Of The Array Phase Induction Logging Tool (apil)

The researched equipment in this dissertation is a new generation one of Array Phase Induction logging. It consists of an array of 5 emitters and 10 receivers, working frequencies are 0.4MHz, 0.8MHz, 1.6MHz, 3.2MHz, 6.4MHz and respectively can provide 5 different depth detecting phase curves. The work of the equipment is based on electromagnetic field theory and undulation theory, and it does not measure the absolute quantity but measure the phase difference of the two signals. The phase difference is related to the conductance of the rocks nearby in the well hole. This approach reduces the trouble of diffusion and widens the conductance mearsuring field. And it reduces the influence of the well hole, slurry on the measured results. And the radial detection depth increases but the vertical resolution does not decrease, so we can obtain the imformation of the original stratum.The dissertation mainly illustrates the Array Phase Induction logging receiver's hardware design and its implementation scheme based on the techniques of faintness signal adjusting and Direct Digtal Synthesis. According to the emphesis and difficulty, the dissertation expatiates on the logic design of the FPGA, the hardware architecture of the DDS design, faintness signal adjusting circuit design and the implementation of winding resonance circuit. The dissertation also gives a brief description of CPU instruction and testing system. This dissertation includes:Chapter 1 gives a introduction of logging and electric logging and introduces the project. Chapter 2 expatiates on the theory of the project and the architecture of project. Chapter 3 gives a discussion in details on signal's picking up from the winding wire and the signal's long distance transmission. The implementation and the architecture of the signal's adjusting circuit are also discussed in this chapter. Chapter 4 mainly discusses the goal of signal generation circuit, the architecture of signal generation circuit, the principle of signal generation circuit and the FPGA's internal logic design, discusses the equipment status control logic and the firmware used to detect the phasic difference. Chapter 5 discusses the debugging, the experiments and something needs to be improved. Chapter 6 is the summary of the dissertation. Experiments show that, the designed receiver satisfied the requirements of Array Phase Induction logging and has been checked and accepted by the project sponsor.