A Suitable Digital Communication Systems, Programmable Logic Device Macrocell Structure And Its Verification

In recent years the use of programmable devices has increased in many areas because they have shorter design and production-cycle times and justify lower-volume production than application-specific integrated circuits (ASICs). Among the many alternatives in programmable devices, Field Programmable Gate Arrays (FPGAs) have shown significant success in recent years because they can provide all the benefits of programmable devices while exceeding the performance of ASICs.This dissertation focuses on analyzing a sort of programmable logic devices macro cell structure basing on digital communication systems. It owns high performance and high use ratio in digital communication systems application.In this paper, we firstly analyse and compare commercial programmable logic devices diversified structure. Then we study a sort of programmable logic devices macro cell structure combining with digital communication systems' characteristic. This macro cell adopts a new mixture logic structure with LUT and MUX, and fast carry logic and cascade chain design, "and" gate design for implementing fast multiply operation, many out ports design, many registers design etc. These measures improve on data processing rate and hard resource reasonable use ratio. Whereafter we validate this macro cell on some digital communication systems' basic modules. The results indicate the macro cell designed have all reached the designing requirement on performance, resource utilization ratio.