FPGA Implementation Of The Equipment Of The Multifunction Vehicle Bus In Train Communication Network

MVB (Multifunction Vehicle Bus) Class 1 device is a kind of network interface unit which is widely used in Train Communication Network (TCN). Nowadays, to transmit lots of control and service information, the new-style locomotive in our country uses TCN mostly. However, the network equipments are mostly imported from abroad. So it is urgent for our country to develop TCN products of independent intellectual property rights.This dissertation mainly focuses on the design of Class 1 devices controller, and adopts a top-down module design method, in which Class 1 device controller is divided into synchronization layer and data processing layer. In Each layer, some functions are realized to send and receive frame, and to extract and store of frame data, respectively.In the Synchronization layer, there are three modules consisted: frame recognition module, Manchester encoding module, and. Manchester coding and frame packaging module. Firstly, in the frame recognition module, the start bit of frame is examined while the type of frame is judged. Then the Manchester coding value is judged in the frame encoding module according to the sample. When sampling, the difficulty is that errors are brought by the non-ideal signals. To enhance the quality of sampling, a multi-spots sampling method combined with bit synchronization is introduced in this dissertation. As non-data symbols are not needed to be coded, the coding circuit is closed for the now-data symbols when coding, thus the non-data symbols can be outputted with its original format.In the data processing layer, the main control unit (MCU) and traffic memory data are designed as the core. The MCU is the core of the controller, in which the received main frame are analyzed then corresponding action is selected according to the commutation mode of the variable. Alternatively, to extract and send the slave frame from the corresponding ports of Traffic Memory, or to prepare to receive the slave frame and write it into Traffic Memory. While in traffic Memory, communication data is stored, appropriate address assignment will Simplify control program. To Simplified the complexity of MCU program, in this dissertation, the port size of Traffic Memory is invariable so that it can traversals the port by a fixed formula to predigest the complexity of MCU program. Besides, as a lot of errors may occur in the process of data transmission because of disturbance and conflict, Cyclic Redundancy Check combined with dual checkout extension is adopted in this dissertation to implement error control of the transmitted data in the design of MCU.Finally, MVB Class 1 device is developed using FPGA and Verilog HDL which is a kind of hardware description language. Recently the device has applied in the SS4G electric locomotive Brake Control Unit and passed the TCN communication test in Railway Academy of Science. The successful development of the Class 1 device establishes a stable foundation for the exploitation of the Bus Administrator and gateway of TCN.