Oscilloscope Acquisition Technology And Lcd Design

AS the front system of real-world analog signals into digital signal processor, Data acquisition system plays a very important role in the modern test technology. the electronic engineers need observing various types of signals for debugging during the designs, and also need the high quality of the data collected from acquisition system. data acquisition technology as the most important part of the oscilloscope, it performance determines indicators of the oscilloscope.In this paper, we use 2G sampling rate handheld oscilloscope which designing by our laboratory as the platform to introduce the 2G acquisition system's overall architecture and data collection processes, application the over-sampling techniques on data acquisition system to improve sampling precision, after plenties of tests, improved a way which can upgrade our acquisition system's precision. First, this article describes the theory of data acquisition technology, 2G data acquisition system with high number of demonstration programs, we make a consistent realization of our system to improve the accuracy of data collection After comparing the commonly ways.Second, this article also describes DMM module design which based on RS232 serial communication in data collection system. it including the hardware design of the DMM module, FPGA design data receiving module, serial communication theory and application of methods in this module.The module can realize automatic and manual selection of two-scale model.Measurement functions include AC / DC voltage, AC / DC current, resistance, diode, on-off test, and capacitors.Finally, the paper also show a new display module design after contrast analysis and feasibility study proposes to the variety of commonly display module. This project use PFGA to generate the signals to control the on-chip SRAM and refresh the LCD panel. This paper described this new method in details such as how to complete the LCD display in the FPGA internal timing of the production, read address generation, single-chip SRAM read and write switch control function.