Design Of H.264 Hardware Decoder

As a new video coding standard, H.264/AVC will bring us high quality visual enjoyment. Accompanied with such enjoyment, the complex calculation of H.264 has brought a big challenge to design of H.264 CODEC. This thesis is born under such circumstance.The target of this thesis is design and implementing a hardware decoder, which support H.264 Main profile level 4. After a brief introduction of basic algorithm of video decoding and SoC design technology, an SoC architecture of H.264 hardware decoder is proposed in this thesis as well as hardware implementation of some video decoding algorithm. Some innovative design such as "Hybrid video decoding architecture", "algorithmic level resource sharing of Inverse Quantization/lnverse Discrete Cosine Transform (IQ/IDCT)unit", "Two-time look up table algorithm" are also proposed in this thesis.After study of hardware/software co-design, hardware/software partition and IP reuse technology, a hardware/software co-design, co-simulation and co-verification flow is proposed here. It has been proved that reasonable hardware/s0ftware partitioning; IP reuse and applying hardware/software co-design technology in our design improved the efficiency and accuracy of our design.Algorithm of IQ/IDCT and Motion vector reconstruction (MVC) was studied here. At last hardware implementation of those parts are also given in this thesis. In order to keep decoding parallelism of the decoder, a ping-pang buffer is used as interface between IQ/IDCT and entropy decoder; using two-time look up table generates quantization parameter of IQ module minimizes the logical resource of look up table in the decoder; Since the algorithm of IDCT and Inverse Hadamard transform (IH) are very similar, and these two transform would not occur at the same time, they are implemented using unified one dimensional fast transform. Logical resource is saved due to the improved algorithm; "Basic address + incremental address" method is used to locate every partition in tree structure motion compensation mode to simplify the calculation of MVC.At last FPGA verification platform is introduced in this thesis as well as the results of design and verification.