Embedded Risc Processor Design, Instruction Pipelining Unit

This paper based on the 32-bit embedded RISC processor design project - "ENOD" of a company, focoused on the instruction pipeline in embedded RISC processor, author finished the design of instruction unit and configurable multiplier.32-bit embedded RISC processor ENOD used SPARC architecture, and used the AMBA bus as interface, so it has high configurability.Instruction pipeline unit is the primary data path in ENOD. As a nuclear module in ENOD, it controls the process of integer instruction executed. Author begin from analyzes the architecture and instruction set of ENOD, discuss the consideration of stage partition and issue strategy, illustrated the details of instruction pipeline unit in ENOD. Researched and analyzed the issues related to pipeline performance as data dependence, control dependence and resource dependence, selected the solution at last. Author analyzed the work and implementation of every stage in instruction pipeline carefully.The hardware multiplier is very complex, located in the critical timing path of the whole chip. For improve the performance of ENOD, based on Radix-4 Booth arithmetic, author designed three multiplier structure, single-cycle, pipeline, multi-cycle for various application fields. According to the operands' width of ENOD, authour selected the multi-cycle as the hardware multiplier in ENOD.The reusable testbench for ENOD has been established, and finished the function simulation for instruction pipeline unit and configurable multiplier of ENOD. Based on SMICO. 35um standard cell, finished logic synthesis and static timing analysis, the max frequency is 100Mhz, fullfil the design goal.The work which this paper had done provided a good way and has great significance for studying the more advanced processors.