Design And Implementation Of 32-bit High Temperature Processor Chip Based On ARMv7 Instruction Set And Its Optimized Multiplier

SoC-equipped embedded systems built with microprocessor chips as the core are widely used in various industries,including deep well detection,image processing,information communication and industrial control.In the microprocessor,the multiplier is the key component for data processing and the core unit for digital signal processing.At present,processors with optimized multipliers can provide hardware acceleration in fields that require a large number of multiplication operations,such as data fusion algorithms,Kalman filtering,and convolutional neural networks.In order to increase the speed of multiplication and reduce the circuit area of the SoC chip,it is necessary to optimize and improve the logic circuit,compression structure and adder of the multiplier.Because the microprocessors under ARM are widely used in embedded system design,this article adopts ARM's open source embedded microprocessor Cortex-M3 core and related peripherals to construct SoC.The core uses ARMv7 instruction set and 32-bit bus.The SoC working clock frequency of this design is 50MHz,and it is interconnected with ROM,RAM,and AHB to APB bus bridge through AHB-lite bus.The APB bus is connected with three sets of UART interfaces,a set of 32-bit GPIO interfaces,SPI interfaces and Watchdog modules.The core comes with Systick Timer.In this paper,the mixed structure of half adder and full adder is improved.3-2 Wallace tree compression structure is used as the compression structure in 32-bit signed and unsigned multipliers.The average multiplication speed of unsigned multipliers is 17.17491ns.Signed multipliers The average multiplication operation speed is 18.121009ns,and all operations are completed within one clock cycle.Two-dimensional 16-bit and 4-dimensional 8-bit vector multipliers are designed to implement vector point multiplication operations,and four multipliers are added to the SoC for applications that require a large number of multiplication and addition operations.Using Altera's FPGA to design a prototype verification platform,test and verify the SoC of this design,it fully shows that all the peripheral devices and processors of the SoC can work normally.Based on the German high temperature 180nm CMOS process library,the software DC and ICC are used to synthesize and layout the SoC of this design,and finally generate the SoC chip layout.