Research And Realization Of SoC Verification Environment Based On VMM

Nowadays, as the SoC chip size and function of the geometric growth,the tra ditional verification techniques are not able to meet the requirement of the project schedule.verification cycle throughout the whole project development is growing continuously and the investment on verification resources are also become much larg er. Hence, verification becomes the bottleneck or the critical path for projects. The huge pressure of validation force verification engineers to break through the traditi onal methods and develop the more and more advanced verification techniques to shorten project time.SystemVerilog has emerged as the leading Hardware Verification Language (HVL) for verifying complex digital logic. On top of SystemVerilog, is the popular Verification Methodology Manual (VMM), which consists of methodology guidelines, class library and VMM Applications package to simplify and standardize the verification infrastructure creating. Based on these methodology guidelines and class library, it is easily to construct the reusable verification environment. It will minimize the overall effort and maintenance.This paper refers to a reusable environment, which is based on VMM. This kind of testbench has good structure and reusability,it can improve the sufficiency and efficiency of verification because it support the function of constraint-randomize, auto-check, coverage-driven,it accelerates the process of the project.With the deep analysis of the source code of the VMM, this article has studied the call mechanism further within VMM simulation system. And on this basis, combined with the guidance of VMM verification methodology, this article has also realized the generation of random stimulus with constraints and directional stimulus, statistic of the coverage, real-time comparison of DUP output data and other automated functions. Meanwhile, functional coverage points can be added into the verification environment at any time. Automated comparison mechanism can be custom-made according to the practical requirements of verification environments. The constraint conditions of the random test vectors can also be changed. All of these functions above maximize the reusability and flexibility of the verification environment. Besides, this article introduces the transaction-level modeling approach, which improves the abstraction level of the verification environment from signal level to transaction level, and hides some of the lower-level details by the way of abstraction. This article has run different test cases, with only modifications of the test scenarios and constraints.This system-level verification platform realized in this article has been applied to the functional verification of a multimedia terminal chip successfully. The final validation results and coverage have both reached the expected target. The big advantage of the VMM verification methodology has also been fully reflected in the entire verification process.