Research On GPS Carrier Tracking In High Dynamic Conditions And Its FPGA Implementation

In the field of astronautics and military use, satellite navigation receivers (installed on rockets and missiles) will sometimes have large speed, acceleration, and even jerk relative to the satellites when they are in high dynamic condition, leading to drastic change of Doppler frequency and serious disorder of the satellite signal tracking system. And normally, special requirements for navigation receivers design under such high dynamic condition are proposed, one of which is the design of carrier signal tracking loop.In order to solve the problem of tracking carrier under high dynamic condition, the carrier tracking algorithm was improved by many researchers. Kalman filter was first used in carrier tracking, and successively researchers put forward the Extended Kalman filter (EKF) carrier tracking algorithm and Unscented Kalman filter (UKF) carrier tracking algorithm, which were of much better performance. But, the UKF design usually assumes that the priori process noise and observation noise are white noise, whose statistical characteristics are known as constants. It is obviously inconsistent with the working background of satellite navigation receivers under high dynamic condition, and the UKF can’t guarantee the convergence and stability in carrier tracking system.To deal with this problem, a master-slaver adaptive UKF (AUKF) method is proposed in this paper. AUKF can adjust the noise covariance, so as to reduce the estimation error of the model and inhibit the divergence of filter. Matlab simulation results show that the carrier tracking algorithm based on AUKF has good stability when the statistical characteristics of the noise change dramatically under high dynamic condition.In order to meet the real-time demands of the carrier tracking under high dynamic condittion, the FPGA design based on AUKF carrier tracking algorithm is implemented in this paper. Some simplification is conducted to the AUKF algorithm to reduce the computation complexity, avoid repeat operation and facilitate the FPGA design. The function and timing of each algorithm modules are tested by ISE simulator. Compared to on the PC platform, the operation speed of the algorithm on the FPGA platform is really much faster.