The Solid Propellant Overload Parameter Storage Test System Based On Fpga

In the process of solid rocket motor, some dynamic parameters of solid propellant grain such as the dependent variable and the overload acceleration play a significant role in the fault detection and the safety assessment of solid rocket motors. Currently, domestic researches on parameter testing of propellant grain under the overload condition are still very rare, and commonly used test methods exists external signal lead wire easily broken problem, fabrication and installation difficulties. Based on this situation, researches on the storage test system aiming at measuring the overload parameters of solid propellers have been carried out.In this dissertation, the system indicators, the design discipline and the general scheme have been proposed based on the surface strain analysis of solid propellant in the actual working conditions, the acceleration signal and the particularity of test conditions. A signal processing circuit is designed based on the electrical characteristics of selected sensors and system performance indicators. Besides, a FPGA controller, an AD converter, a USB communication controller and a memory circuit are also designed. Various controllable modules of on-chip hardware circuits are programmed by using the Verilog hardware description language under the QuartusII9.0software environment. And a software interface for the host computer is developed using LabVIEW8.6, which realize the programmable gain amplification for the test system, the automatic bridge balance, the internal trigger set and the data read testing. In addition, it also has the function of gathering large strain signals in three channels and acceleration signals. A reasonable and effective power supply circuit is also designed to ensure the device to work properly during the test. And a mechanical shell has been designed using SolidWorks2008to meet the requirements for the test environment and the device under impact. Furthermore, the protection and buffering capacity of circuit board are analyzed and designed based on ANS YS simulation analysis. And a reasonable conversion on each interface is made to ensure that the interface of the device matches with the outside communication interface. Combined with signal generator, the drop hammer signal generator and the method of parallel resistance, both acceleration and strain are debugged and assessment by this device. The results of tests show that the memory test device designed is feasible and effective, which has practical engineering value. Besides, it also provides an effective testing method for the fault detection and the safety assessment of the solid engine.