Design And Implementation Of A 8bits Low Offset Voltage 1Gsps Flash ADC In 0.13um CMOS

With the development of integrated process, high-speed ADC (Analog-to-Digital Converter, ADC) has been used widely in video, wireless communications, military and other fields, and it becomes more and more cost effective, and the trends of the current mainstream of the A/D converter is high-speed, high resolution and low-power. Especially in applications such as the oscilloscope, the hard disk drive read channel, and wireless communication, and higher conversion-rate of A/D converter is required.Based on 0.13μm CMOS technology, a 8-bit low offset voltage flash ADC was designed and implemented, the maximum sampling rate of the ADC is 1Gsps. The main contents of the research work include the following:1. In-depth study the structure and performance characteristics of various high-speed analog-digital converter, to lay a good foundation for the high-speed ADC.2. A new 8-bit Flash ADC structure is adopted. First, the flash-based interpolation A/D converter without sample/hold circuit is used, which not only can complete a conversion in a single clock cycle and adopts the resistance interpolation mode,compared to traditional structure,the requred perfermance of the comparator is lowed; Secondly, a pipline mode using the same clock improve the conversion rate of the chip; Finally, a single-stage pre-amplifier circuit was adopted to eliminate the offset voltage of the comparator, and further improve the conversion rate of the converter.3. In-depth study the measure to minimize the offset voltage in the the operational amplifier circuit in the condition of maintain the sampling rate and accuracy. By analysis we know the main factors lead to the offset of the operational amplifier circuit including the active area and transconductance of the input transistors: the input transistor transconductance was minimized in the circuit design, that the output is insensitive to the offset; the input transistor without multifinger mode was used in the layout, to reduce the area of the active area, and further reduce the offset voltage through the layout technology.4. Study the main affecting factors for the offset of the comparator circuit. By the method of pre-amplification, the difference of the input voltage was amplified, which reduces the impact on the offset voltage of the comparator.5. A 8 bits 1Gsps high-speed ADC was implemented in a 0.13μm CMOS. The area of the ADC is 4.792mm2. The simulation results of layout showed that the maximum value of the INL and DNL were less than 0.6LSB and 0.4LSB respectively, SNR was 46.8dB, ENOB was 7.5bit, power consumption was less than 800mW when the input signal was 16.6MHz at sampling rate of 1Gsps, which meet the requirements of the design.