| With the development of digital audio and video technology, it has become acommon practice to implement multiple audio and video functionalities on a singlehardware platform. This thesis focuses on how to achieve this goal from the angle ofreconfigurable computing technology and proposes a general architecture for digitalaudio and video applications, which is helpful to promote a wider adoption ofreconfigurable computing technologies in consumer electronics field.Firstly, a basic introduction is given first on the digital audio and videotechnologies used today, as well as their evolving process, which is followed by adetailed explanation to their underlying theories and implementation techniques.Currently, vast majorities of audio and video products are using either CPU-based orASIC-based solutions. Each of them has some advantages over the other, but at thesame time, has some limitations. For the CPU-based solutions, they are very flexible,but have lower processing efficiencies and require high frequency CPUs andconsumes more power. Meanwhile, the ASIC-based solutions have higher processingefficiencies and can provide higher performance with less power consumptions, buttheir functionality cannot be changed easily once they are manufactured.Reconfigurable computing is a promising technology because it can provide bothgood flexibility and high performance, which has the potentiality to satisfy the toughrequirements that digital audio and video applications have imposed on hardwareplatforms.Next, a general architecture for digital audio and video processing is proposedbased on the studies of reconfigurable computing technologies and the most recentresearch progress in this field. Such architecture still uses a CPU as the core toperform various computation and controlling tasks, but it also has reconfigurableco-processor that is connected to CPU through high speed local bus and can bereconfigured to complete some different tasks that are not suitable for CPU, such ascomputation-intensive tasks like video encoding and decoding. Some importantdesign problems, including the hardware/software co-design methodology,implementation of the co-processor, and data transfer over the high speed local bus,are discussed in detail.To demonstrate the feasibility of the proposed architecture, two concrete samplesystem designs are implemented. MEPG-2video decoder and MP3audio decoder are not used for this purpose due to the great effort required to implement them and thelimited time and resources available. The first sample design is used to display BMPimages on an external monitor, considering that displaying images are an essentialpart for MPEG-2decoder. For the same reason, the second design uses radio as theexample to verify the architecture design for MP3function. The final experimentresults show that the proposed architecture is feasible. |
