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Based On Dpll And Gps Synchronous Signal Synthesis And Timing System Research

Posted on:2014-01-05Degree:MasterType:Thesis
Country:ChinaCandidate:Q H GuoFull Text:PDF
GTID:2248330395982589Subject:Physical Electronics
Abstract/Summary:PDF Full Text Request
Synchronous clock signal is very important for the electronic technology and product, especially in the FM sound sync-broadcasting. A Sync Signal Synthesis and Time Service Technology based on GPS and DPLL is presented in the thesis. It will be used in synchronous broadcasting.Frequency synthesis technology, Digital Phase Locked Loop theory and GPS time service technology is firstly analyzed in the thesis. DPLL chip AD9548locks1PPS which comes from GPS OEM board for synchronizing signal synthesis. FPGA is the system master control chip. Hardware circuit includes the FPGA driver system circuit, AD9548system circuit, filter circuit, peak to peak value detection circuit and so on.System gets the time by decoding GPS OEM board data stream from FPGA, fix the real-time by1PPS and display them on the LCD. This section includes UART transceiver module design, NEMA0183data flow decoding, time correction, LCD driver, etc.The synchronous signal is generated by AD9548, which is configured by FPGA. Synthetic signal synchronization is realized through configuring critical resisters of AD9548to lock GPS OEM Board1PPS. In addition, the FPGA measure synthetic signal frequency and peak to peak value and display them on LCD.Compare the Equal Precision Frequency Measurement and Common Frequency measurement by strict theoretical analysis. The paper quantitatively studies the Equal Precision Frequency Measuring error, and points out that the equal precision frequency measuring method is not applied all the time, and corrected some misunderstandings in some literature.
Keywords/Search Tags:DPLL, Frequency Synthesis, FPGA, GPS Time ServiceEqual precision Frequency Measurement
PDF Full Text Request
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