Research Of Synchronization Module In Digital Substation

With the development of digital substation, higher requirements for thesynchronous clock accuracy and stability have been put forward by equipments at alllevels in the substation. The accurate data synchronization is even more important formerging units in the digital substation, which work as interval layer and stationcontrol layer device data source. Traditionally merging units ensure samplingsynchronization by passing second pulse, which can hardly meet the demand foraccuracy in the digital substation. In order to solve this problem, a suitable mergingunit clock synchronization module is designed in accordance with the IEEE1588network time protocol.It is considered that synchronization demo is controlled by MCU of merging unit.Thus, Altera’s chip EP3C25Q240C8is selected as MCU. As a typical FPGA chip,chip EP3C25Q240C8, which has low power consumption, large capacity,high-performance, can avoid a different controller clock synchronization module andmerging unit signal transmission error. NI’s chip DP83640, which records theaccurate time information of the physical layer by hardware timestamps, is selected asan Ethernet controller, thereby reducing errors in the transmission process. The designis complete auxiliary module, such as the power supply module and internet module,and PCB design is proposed.In QuartusⅡ10.1experimental platform, software program based on languageverilog is worked out. The IEEE1588model’s master-slave clock module is built, theprogram of slave clock’s time adjutancy is proposed. The test experimental isdesigned, the effect of the proposed clock synchronization module is researched, andthe effect of clock synchronization module is tested.