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Bottom Module Design Of Standardized Bus Interface For Satellite Electronics

Posted on:2013-04-24Degree:MasterType:Thesis
Country:ChinaCandidate:L ZhangFull Text:PDF
GTID:2252330392968066Subject:Control Science and Engineering
Abstract/Summary:PDF Full Text Request
Standardized bus interface for satellite electronics is the precondition to achievingOperationally Responsive Space. It has strategic significance for space exploration andintelligence collection in the future. Improving the speed of response is one of the keypoints to winning in the future war. It is very important to ensure the responsive satellitebeing rapidly designed, manufactured, tested and launched. Research of satelliteelectronic bus interface standardization is focused by many countries.The bottom communication module of standardized bus interface is designed inthis paper. FPGA is used to implement the basic functions of the bottom module. Thefollowing work is completed: firstly, by analyzing the designed standardized busprotocol, a reasonable design is achieved. And suitable bus transceivers are chosen.RS485chip is used as the low-speed channel transceiver and M-LVDS chip is used asthe100Mbps high speed channel transceiver; Secondly, the top-down design method isadopted to design the bottom module. The design is achieved respectively by dividingthe bottom module into several sub-modules. This method improved the designefficiency and flexibility, saved design time and improved the system capability andversatility. It is easily to joint with other module of the interface. When the errors arefound, they can be modified easily. The main sub-modules include the transmissionmodule, receiver module, frame/deframe module,8b/10b coder/decoder module.Thirdly, the basic principles of clock data recovery and related issues are introduced,and the basic work principles of Phase-Locked Loop(PLL) andDelay-Locked-Loop(DLL) are elaborated. The oversampling method is chosen, and thetwo phase-shift clocks created by the Digital Clock Management is used in FPGA assampling clock to achieve the function of data recovery. Finally, a integrated test systemis used to verify the design.The experiment showed that the bottom module design of the standardized businterface in this paper was reasonable and effective, it can achieve the basic functions ofthe standardized bus interface.
Keywords/Search Tags:standardized bus interface, module design, clock data recovery
PDF Full Text Request
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