Design And Implementation Of The Instruction Dispatch Unit With Emulation/Test Support

As the key part of the electronic system, Digital Signal Processor(DSP) are widely used inmany fields such as spaceflight, aviation, radar, sonar, communications, and householdappliances. With the increasing demand of high performance of signal acquisition and processing,the DSP’s integration is becoming more and more complex, bringing a big challenge to theon-chip-debugging. It becomes an important issue of DSP research that how to improve thedevelopment efficiency and chip quality through on-chip debug system.YHFT-Matrix DSP is a high-performance32-bit vector DSP designed by NationalUniversity of Defense Technology independenently, which can work at500MHz. It is a VeryLong Instruction Word(VLIW) architecture with a16-bit/32-bit variable-length RISC instructionset. A maximum of ten instructions can be issued in every clock cycle.Based on the YHFT-Matrix DSP, this dissertation focuses on the design andimplementation of the instruction dispatch unit with Emulation/Test support. The main researchwork and innovations are as follows:After a deep investigation of the YHFT-Matrix DSP’s architecture, instruction set and theinstruction pipeline, this paper fullfills the design and optimization of a high performanceinstruction dispatch unit with the support of instruction bypass fetch and cross-boundary executepackage’s dispatch.This dissertation proposes a novel instruction-parallel-dispatch method, which breakstiming restrictions caused by the instruction dispatch.Based on the features of YHFT-Matrix DSP’s memory resources, instruction format, andpipeline structure, this dissertation propose a Emulation/Test method, witch support hardware/software breakpoints in the dispatch unit, the access of the on-chip resource, the control of thepipeline, and the statistics of14key events or signals.This dissertation also proposes a novel Softwire-Break-Point mechanism, which meets therequirement of the16-bit/32-bit variable-length instruction set.A fully verification of the design is carried out based on the simulation and formalverification methods.This dissertation also builts a FPGA-based prototype of YHFT-Matrix DSP.With the hardware/software joint debug, we analysis various situations to modify the RTLdesign to meet the design requirements.Now the chip has been successfully taped out and tested. All functions of the dispatch unitwork properly, and all Emulation/Test functions meet the design requirements.