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The Design And Optimization Of Instruction Control Unit On High Performance DSP

Posted on:2005-07-30Degree:MasterType:Thesis
Country:ChinaCandidate:Q SunFull Text:PDF
GTID:2168360155471831Subject:Computer Science and Technology
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DSP (Digital Signal Processor) is a special processor for digital signal processing, which is also the key technology in this domain. DSPs have been developed for 26 years since the first DSP was invented in 1978. Now DSPs have been widely used in domains such like wireless communication, voice recognition, global position system (GPS), vehicle navigation, military radar and weapon control system. More new applications, such as broad band(cable modem, xDSL, Gigabit Ethernet, 10Gb Ethernet), multimedia (MP3, MP4,DVD,digital camera, digital video recorder),VOD, video meeting and VoIP are demanding more sophisticated DSPs. Therefore, developing YHFT-D4 is significant both in seizing hold of the frontier of technology and market and in protecting national information security and military information security.YHFT-D4 is a 32-bit fix-point DSP of high performance, which uses VLIW structure. It has 8 functional units sharing 32 general purpose registers. It can issue 8 32-bit instructions in parallel at the most. It also integrated abundant on-chip peripherals. YHFT-DX structure proposed in this paper is an improvement of YHFT-D4.The functionality of Instruction Control Unit is to fetch instructions from external memories and to dispatch them to Execution Units. The key point of YHFT-DX's Instruction Control Unit is whether it can deliver uninterrupted parallel instruction stream of high density. To implement uninterrupted parallel instruction stream delivery, a prefetch mechanism of fetch unit level was researched and designed, which greatly improved the pipeline efficiency. The time of executing standard testbench is 5.15% shorter on YHFT-DX than that on YHFT-D4. To support high-density instruction stream, a Fetch Pack Boundary-Span Dispatch mechanism was researched and designed, which improved the code density of about 15%. At the same time, it improved the efficiency of on-chip memories and reduced L1P miss rate.Standard cell based semi-custom design flow and methodology was explored in this paper too. DC (Design Compiler, a synthesis tool of Synopsys) was used to synthesize and to optimize the Instruction Control Unit at Artisan's 0.18μm process. And the result shows that the frequency of Instruction Control Unit is up to 200MHz before P&R and is up to 150MHz after P&R.
Keywords/Search Tags:YHFT-D4, YHFT-DX, DSP, VLIW, fetch, dispatch, prefech, Boundary-Span Dispatch, synthesis, verification
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