The Interconnect Test For FPGA Chip

The development of integrated circuit technology make the field-programmablegate array (FPGA) have larger scale、stronger functions and richer internal resources aswell as greater testing difficulty. On the chip, programmable interconnect resourcewhich bear the interconnection and the signal transmission between logic blocks is themost complicated and largest module. It accounts for the proportion of the resources ofthe whole chip even more than70%. The programmable interconnect resource’s highflexibility and large scale make its testing method has always been the emphasis anddifficulty in the FPGA testing method study field. The study object of this paper is theinterconnect test.Firstly this paper described the structure’s feature of the internal interconnectresources in detail as well as the interconnection’s relationship. The description whichprovides support for the follow-up study focus on the single line, hex line and longline’s connection and switch matrix’s circuit structure. And according to the circuitstructure，a set of fault model have been put forward. The fault model has coveredseveral common failure types basically which often appeared in the actual circuit andalso has been optimized at the same time. Then a series of testing paths have beendesigned after considering the fault model and interconnection law. In addition tomeeting the demand of resource coverage and fault coverage, this series of testing pathis also very practical and easy to implement at the same time. Finally，two kind oftesting plan have been designed for the purpose of production test as well as diagnostictest and the interconnect test have been completed actually. The experimental resultsshow that this testing scheme not only can obtain higher resources coverage and faultcoverage, but also has simple and practical features. So, this interconnect testing hasachieved the expected result.