Research And Design Of FPGA CAN Bus Controller

CAN (Controller Area Network) is one kind of field buses, which are widely used in current automatic control field. It is a type of fully digital, multi-master and asynchronous serial buses and only defines physical layer and data link layer in OSI seven-layer model. Since it has the features of efficient message filtering mechanism, error detecting and communication recovering mechanism, communication distance adjustable with baud rate, convenient application layer interface and so on, presently CAN bus has a rapid development towards more fields besides of automotive industry, industrial control, intelligent community.CAN bus controllers available in the market are not easily integrated in embedded system because they are customized with all kinds of standards and their interfaces are fixed. FPGA, which now plays a more and more important role in embedded design field, puts forward the requirement of both soft and hard programmable. Soft cores embedded into FPGA become the need of embedded systems. So making CAN bus controller function standardized into soft core and putting it into IP library will meet the requirement well. In order to satisfy different embedded need, interface can be designed flexibly at the same time.The purpose of this paper is to complete the front-end design of CAN bus controller and RTL level design of data link layer in CAN2.0A protocol by using VHDL. Design of controller uses top-down method. Firstly, we split the controller into several modules which are independent but associated with each other. Secondly, design ideas and steps are further elaborated. Controller is split into three main functional modules, including registers control module, bit timing logical module and bit stream processor module. In order to improve the functional integration of FPGA, the controller applies interface of PicoBlaze which is eight-bit embedded soft core of Xilinx instead of that of traditional51. Design of registers refers to PHILIPS’ SJA1000. Bit timing logic is made of bit timing and synchronization. Bit stream processor is made of CRC checking part, acceptance filter part, RXFIFO part and communication fault processing part. Design method of each functional module is designing with functional simulating using Modelsim software simultaneously. Finally, we compile the entire codes which have passed functional simulation into bit stream file and download it to Spartan3E of Nexys2development board. Test results show that the controller has achieved the design requirement.There are a lot of system resources in FPGA. Incorporating more functions with CAN bus controller in the future lays the foundation for SOPC in FPGA.