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On Soc System Based On Mcu And Can Controller Design

Posted on:2013-08-27Degree:MasterType:Thesis
Country:ChinaCandidate:L Q LiangFull Text:PDF
GTID:2248330374477604Subject:Computer application technology
Abstract/Summary:PDF Full Text Request
Nowadays embedded system have been ubiquitous, theequipment based on embedded system have soaked into intruductionarea, entertainment, medical facility,military affairs and so on.As VLSI(Very Large Scale Integrated circuits) lay a foundation for embeddedsystem,high performance micron process for example CPU,DSP,SOC. Tonormal embedded system designer,especially nationial development,the most of system project used to design with board level method. Inthese years the technique of VDSM-Very Deep Subnicron andIP-Intellectual Property reuseare more and more mature, the apply ofSystem-On-a-Chip lead to revolution in the area of embedded system.This design that mentioned in paper aims to SOC system thatintegrate CAN bus controller and MCU that is widly applied in carelectrical equipment and industrial control field. It is different with nowimplemention method of CAN bus system-one board include at leastthree chips of MCU plus CAN controller plus CAN transceiver.My designSOC contain8-bit MCU、RAM、ROM、GPIO、counter/timer、Interruptcontroller、CAN controller、Wishbone bus and so on modules. Theimplemention is based on Cyclone series FPGA Ep2C70F896C6Nhardware,and program language use Veriloge hareware programlanguage, on software we choose quartus29.1integrationdevelopment environment, include compile tool, route and place,filter…,In the respect of test stratery,I choose affair level verificationmethod to programm testbench. This testbech have been used in thequalification of this soc design in Modelsim SE platform. Test resultpresent the design can meet requirment of CAN bus communicationunder two modes of Basic CAN and Peli CAN.The advantage of this system-on-a-chip strategy, compared withsystem on board design, are smaller size, high integration degree,minimum of trasfer delay, static power resume degrade fromboard level to chip level(TDP). This system use minimum design strategy,have save a lot of hardware resource, the biggest feature is low-power,small size. This design have best benefit in the situation of volum andspace limited. High real-time characteristic need to be highlighted, thiscome from minimum transfer delay between conductors. There arebetter EMI and EMC effect. We use hardware link to realize CAN transferlevel protocol, the result simplify the communication protocol softwareprogramming, meanwhile cut down CPU workload. this will be benefitto more high performance CAN embedded system development infuture.
Keywords/Search Tags:Embedded System, SOC, CAN2.0Controller, FPGA, STA, Testbench
PDF Full Text Request
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