Research And Implementation Of Algorithm For H.264Video Coding Based On FPGA

H.264is a new generation of video coding standards jointly developed by theITU-T Video Coding Experts Group and ISO/IEC Moving Picture Experts Group.As it contains many advanced video compression encoding methods, compared withthe conventional standard,H.264can save about50%of the bit rate in the case of thesame encoding quality. In this way, H.264not only obtains a high coding efficiencyand high compression ratio, but also has better network adaptability. Therefore, H.264is widely used in video conferencing, video telephony, wireless communications,telemedicine, digital TV broadcasts, streaming media.By a large number of experiments and analysis about H.264algorithm, it wasfound that the motion estimation is the largest part of the entire coding algorithmcomputation process. That is to say, the motion estimation efficiency directlydetermines the efficiency of the entire coding system. Thus, a study of motionestimation search algorithm which has high search speed, high precision, and ease ofhardware implementation has become a priority in the field of video encoding.This article briefly describes the video coding standard development, and detailsthe H.264codec standard basic principles, grade and key technologies. In addition, wedeeply study the principles, steps and even advantages and disadvantages of severalstandard search algorithms in motion estimation technique.Based on the principle of unsymmetrical-cross multi-hexagon-grid search(UMHexagonS), This paper, combining the advantages and disadvantages of eachstandard algorithm, proposes a hybrid hexagon search algorithm, which is mixed withUMHexagonS and the other three search algorithms. The search algorithm can givefull play to the characteristics of the algorithm itself and achieve the complementaryadvantages, so it improves the search speed While maintaining high search accuracy.In order to improve the processing speed of the design and reduce the adverseeffects of motion estimation algorithm complexity on real-time processing, we propose a parallel pipelined hardware structure, so that the four algorithms can beexecuted in parallel.Meanwhile, the use of an effective data transmission architectureavoids reading data repeatedly, reduces the amount of data storage, thereby, furtherimproves the search speed of the design.Finally, the use of hardware description language Verilog HDL realize thehardware structure of the algorithm in the FPGA. Comprehensive simulation resultsshow that this design can significantly improve search speed, lower share of theresources of logic gates, and verifies the correctness of the design.