With the rapid development of EDA technology, The FPGA is widely used by the designer because of simplify of programming language and better flexibility and super ability of parallel computing. In practical application of FPGA, data need transfer between the FPGA and PC.But now FPGA chip has not the function module of asynchronous serial communication in the chip’s internal. Using UART chips can solve this problem. But there are a number of deficiencies in the use process, such as the poor portability, the data transmission speed is slow, more pins and so on, and the range of UART chip application is limited, Therefore, this paper design an UART function interface, which is based on FPGA.The design is based on the platform of Quartus Ⅱ 12.0 in this paper, and using the design method of top-down. The bottom of the sub module is respectively the module of baud rate, the module of start bit detection, the module of FIFO, sending module, and receiving module. In addition, the module of receiving interface and sending interface are function encapsulation to receiving module and sending module. The main purpose of this design is to ensure the receiving module and sending module can be better to be used under different conditions. This paper does not use the method of state machine in the design of sending module and receiving module, using the write method is similar to C language.It can not only improve the readability of the module, but also reflect the characteristic of FPGA timing. The design of each model contains functional analysis and code, and they are ok under the simulation of the Modelsim. Finally, in order to ensure that the design of the UART module can be used, the receiving interface module and the sending module of the bit-flow information are downloaded to the development board to test of board level.Through the simulation and the test of board level can be explained, the function of UART module is designed to meet the use requirements in this paper, so the design achieve the expected goal. |