As the IC is getting more and more complex, especially in the SoC technology and IP reuse technology is becoming more and more mature, how to verify the function of the chip effectively becomes critical. Under this background. Based on the SystemVerilog, VMM verification method was proposed. The VMM verification method has high efficiency, easy maintenance and reuse characteristics which made it become more and more popular in engineers. Has considerable theoretical significance and practical significance.This paper was based on SystemVerilog and VMM. First of all, this paper summarized seven features of SystemVerilog, the seven features are: constrained random excitation, reusability, interface, testcases, function coverage, DPI, assertion and specific internal connection mechanism. After that introduced the basic flow based on VMM. VMM verification methodology provides the standard library, so this paper also introduced the standard library of VMM.This paper has built a testbench based on VMM, So the knowledge of DUT is necessary on verification. After introduced VMM, this paper introduced the The overall architecture of DUT and the function of the modules of DUT. The DUT includes: receive module, send module, port state machine and flow control module.Based on the detail function of DUT, the paper also put forward the overall architecture of testbench and the detail function of the modules. Intruduced the detail function of data class, interface, config class, generator class, driver class, monitor class, callbacks and the environment class. At the end of this paper introduced the testcase based on the environment, and also introduced the VCS and how to use it.Analysed the results of VCS simulation.Through personal practice, VMM can effectively improve the verification efficiency, and also shorten the development cycle. The testbench based on VMM Has high reusability, it also can be used on other DUT. Through the preparation of extension and testcase, which can has more functions. |