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Pcmcia Bus-functional Model And Validation Of Soft-core, Of The Bridge

Posted on:2008-07-07Degree:MasterType:Thesis
Country:ChinaCandidate:X LiFull Text:PDF
GTID:2208360215950161Subject:Information and Communication Engineering
Abstract/Summary:PDF Full Text Request
Along with the increasing of the Integrated Circuit's scale, verification is becoming the hardest and the most challenging part of IC design. 80% of workload and resource in IC design is devoted to verification. But till today, verification methodology still lags behind the increasing of IC's scale. Therefore, improving verification methodology is becoming one of the research focuses. And improving verification efficiency is also a major idea in this paper.Abstract is the most important method to improving verification efficiency. Through abstract, the verification engineer could pay their attentions from low level signals to the transaction level. Thus establishing verification environment, coding verification stimuluses and checking the verification outputs become easier and more convenient. The other benefit of abstract is that it could improve the reusability of the verification elements.To verify the AHB-PC Card Bridge IP core, this paper designs PC Card Bus Function Model through abstract. And base on it, this paper sets up Utility Routines. They are of three different layers, and providing more complex tasks. By using them, the verification efficiency is enhanced.Besides abstract, this paper also uses other methods to improve verification efficiency, like verification automation etc.At the backside of this paper, it analyses the principle of parallel simulation, and discussing how to avoid the negative effects of this principle when establishing the testbenches. All of the methods used in verification helped us save a lot of time. And at last we acquired a good result.The methods discussing in this paper also fit for the need of other IC's verification. The established Bus Function Models and Utility Routines are reusable.
Keywords/Search Tags:Verification Efficiency, Bus Function Model, Testcase, Testbench, Verification Automation
PDF Full Text Request
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