Design Of The Verification Testbench For FSK Module Based On UVM

As the Io T chips market expands,the competition becomes fiercer.The developments of Io T chips are accelerated with a high speed.Meanwhile,the verificaion technology is more difficult than ever due to the functionality and complexity of chips.It is not sufficient for the scale of the present chips by the traditional verification methods,such as direct testing.Now,verification technology is becoming a bottleneck of the development of microelectronics.The completence and effiicence of verification are important to the chip development cycle and cost.Thus,verification technologies develop rapidly to be adapted to the chip design and scale.Various verification methodologies has been continuously updated.Universal Verification Methodology(UVM)inherits the advantages of other verification methodologies and overcomes their disadvantages.UVM gradually becomes the development direction of verification methodology based on its advantage.At first,the structure and function of FSK algorithm module was analyzed in the paper.The FSK algorithm module is divided into two parts: transmitter and receiver.The transmitter mainly contains frame setting function,encoding function,interleaving function,whitening function and FSK modulation function.The receiver mainly includes packet detection function,carrier frequency offset estimation function,frame synchronization function and packet parsing function.According to the function of the algorithm module,the corresponding verification test points are decomposed,and the overall verification scheme is formulated.Then UVM validation methodology is used to complete the functional verification of FSK algorithm module.Firstly,the verification platform was built,and the components of the verification platform were designed,including interface,sequencer,driver,monitor,agent,reference model,scoreboard,environment,etc.As one of the components of the verification testbench,the main function of the scoreboard is to collect the output of the reference model and the design under test,and carry out data comparison.The scoreboard was implemented automatic comparison by implementing the sequence comparison function.However,the transactions output by the de-interleaving module in the FSK algorithm module may be disordered,but each transaction must be correct.Therefore,a function of multi-data stream comparision was realized by the design of the scoreboard in this paper.The design took into account the function of general sequential comparison,and realized automatic comparison.In addition,the comparison function,internal port connection,and external port connection were divided into three parts during the design of the scoreboard.The comparison function and internal port connection were encapsulated and multiplexed as a general component module.With this design,automatic comparsion can be implemented by connecting the expternal ports to the scoreboard in other projects.It improvs the verification efficience by implementing the reuse of verification environment components.These two points are also the technical innovations of this project.After the verification environment was set up,use System Verilog to write test cases for simulation.After running a large number of test cases,the simulation results showed that the code coverage and function coverage of FSK module verification based on UVM verification platform reach 100%,and reach the design target.The UVM verification platform constructed in this paper not only covered all functional test points of FSK module,but also reflected the completeness of verification.It realizeed the reuse of verification components,which greatly improves the efficiency of verification.This paper provides a good reference for the design of verification platform for other algorithm modules.