Verification Of 128-Bit Processor Local Bus Based On UVM

This paper describes designing a UVM testbench for 128-Bit Processor Local Bus(PLB)to simulate and verify the correctness of the various functions.The verification requires code coverage up to 95%and functional coverage up to 100%.With the rapid development of semiconductor technology and the improvement of the design capability of integrated circuit(IC),the scale of integrated circuit design is increasing and the structure becomes more and more complicated.Verification is an important part of the chip development process,of which working time have accounted for about 70%of the entire chip development cycle.The traditional testbench is not very reusable.It takes too much time to build a testbench and it is not easy to modify and maintain this kind of testbench.Universal Verification Methodology(UVM)greatly improves the efficiency of building a testbench because of its high reusability.UVM can provide a set of classes based on SystemVerilog.Verification engineers can design a standard structured testbench starting with the predefined classes.This design builds a UVM testbench of 128-Bit Processor Local Bus.It greatly reduces the time to build testbench and the efficiency of verification is improved.This paper introduces the background and the source of the PLB's UVM testbench,the current research situation at home and abroad,main work and the paper and the structure of this paper.This paper mainly introduces the importance of verification for the IC design,the development of verification method,the origin and development of UVM,the advantages of UVM,main work and the structure of this paper.It introduces the composition of the general UVM testbench.This paper introduces UVM testbench,the components of UVM testbench,the functions of each component,the working principle of UVM testbench,and some UVM mechanism which is used.The important signals and operating modes of the PLB module are studied.It mainly describes the introduction of PLB,the working principle of PLB,some important signals of PLB,the different working modes of PLB,and the timing diagram of each working mode.The construction of PLB's UVM testbench is studied.This paper mainly discusses the overall architecture and working principle of PLB's UVM testbench,the selection and use of specific components of PLB's UVM testbench,the definition of interface,the deal of original design code,and the design of the top of the verification environment.The results of the PLB's UVM testbench are analyzed.This paper mainly analyzes the PLB simulation waveforms in different working modes,the results of the comparison of the scoreboards of the UVM testbench and the generated coverage reports.Finally,it is a summary of this paper.We can make the conclusion,PLB's UVM testbench simulation and verification are correct,the coverage meets the requirements,and PLB design code is correct.This design simulates the PLB's UVM testbench and the simulation waveforms match the corresponding timing diagrams in the specification,which leads to the conclusion that the functions of PLB design code are generally correct.In the UVM testbench,the scoreboard comparison results are the same.It can be concluded that the PLB design code is completely correct and consistent with the description of the specification.At the same time,the coverage has reached the requirements for verification,indicating that the degree of verification has met the requirements and the verification is valid.