Design And Co-Verification Of Multi-core Processor Based On Network-on-Chip

As the density of VLSI increases, the complexity of the components in a system also increases significantly. For adapting the pressure of higher operating frequency and shorter time to market oriented time,today semiconductor industry requires is hopefully providing more and more Multiple Processor System on Chip structures. However, after the quantity of the processors increases to a certain degree, traditional communication methods based on bus are unable to satisfy the development demands of future MP-SoC in performance, power, timing closure convergence and expandability etc. In order to meet the challenge of the next generation of system design, recently, one structured assemble and expandable interconnection architecture---Network on chip is proposed for decreasing the complexity of the communication problems on chip.In The study work of this thesis, article is tothose designed and realized are one expandable Multi-core processor platform, including the analysis and selection of the NOC architecture, the realization in the hardware implement of the NOC architecture, as well as the co-verification and performance analysis. The design includes the design of the Communication between cores and the design of the master core and slaver core controlment. For the Communication between cores, this article employs the NoC mode Compared to the traditional shared bus on chip, NoC has the advantages of broader communication band, stronger expandability, and support the reconfiguration of design reuse etc For the design of the Communication between cores, this article uses the double-loop topological structure, packet switching and the dimension ordered routing algorithm as the design protocol of NoC,which protocol not only consuming fewer resource, with a smaller data transmission delay but also lacking of deadlock prolems; In terms of arbitration design, round robin priority is employed, master ports use polling access mode, avoding other master ports always in a wait state For To the design of the master core and slaver core controlment, this article uses one master core is arranged to control on/offall of the other fifteen slaver cores in this thesis, the protocol can determine the number of the cores running according to loading, so thas to increaseing the efficiency and decreaseing the power consumption.In verification section, the Co-verification and performance analysis are carried out on the designed NOC. For the Co-verification, we layed put emphasis on discussing two recently widely used hardware/software co-verification protocols:the co-verification based on simulation platform and the co-verification based on FPGA platform This focuses on the project of NOC hardware and software co-verification system, including hardware design, software design,simulation platform design and transfer technology,debug technology. Co-verification is made to ensure that the System level chip hardware and software design is correct, verify the correctness of System level chip NOC communications networks, software and hardware interface function and timing, It can achieve be conducted to learn the possibility of running the software the hardware before chip-out, reducing the risk of the project. Finally, For in the performance analysis, 16 cores NOC logic loops of this design present on the 16 Virtex-7 XC7A200T devices areto achieveimplemented, The system can operate at a stable operating frequency of 100M, running the matrix multiplication test program (Matrix multiplication test program), whichis runned to find that the acceleration rate isspeedup to be 15.5.This paper studies the NOC Communication Design, Focused on the design of routing nodes, arbitration, etc; According to the working characteristics of the system, the architectural functions has been verification on the platform of co-verification,, indicating NOC structure has good scalability and high performance.