Design Of AFDX End System And Application Study On UVM

AFDX End System is an important part of the new generation aviation data bus AFDX system, and it is a key technology to realize that subsystems establish connection with the AFDX network and communication in subsystems. With the widespread use of AFDX system in new types of aircraft, it is more and more important to research how to design and verify the end system. Hardware circuit designs of AFDX end system and the verification by building testbench based on UVM methodology are presented in this paper.As designing hardware circuits of the end system, W5100 network module is chosen to achieve the data communication between the end system and network, and the FPGA minimum system board is chosen to control receiving or transmitting of data and the state of W5100 chip. By building hierarchical testbench based on UVM methodology, the RTL level verification of the end system is completed with some industry advanced verification techniques, such as the constrained random test technique, process synchronization technique and SVA assertions. The coverage data are collected and analyzed in verification. The application study about testbench base on UVM in actual verification is done on the basis of coverage analysis reports.The traditional testbench has the disadvantage of simple structure, low reusability and poor verification efficiency. As for verification functions of the UVM testbench in this paper are refined and separated, we just need to modify certain function modules of the testbench so as to verify the different designs, which greatly enhances the reusability of the testbench. The use of constrained random test and SVA assertion techniques can save a lot of time and energy in the verification process and improve the quality and efficiency of the testbench.