Logic Design And Verification Of 1394 Bus Contol Node Based On The Actel FPGA

In recent years, avionics has made rapid progress. Traditional IEEE1394 B bus in terms of performance and architectures had not be meet the avionics system for data transmission timeliness, certainty and stability requirements. SAE organization after re-cut and limit the IEEE1394 B bus, formation of the current system is more suitable for avionics SAE AS5643 protocol. The design is based on the AS5643 protocol for avionics system bus control node exploring.Depending on the AS5643 protocol, this paper completed the design and implementation of an FPGA-based AS5643 protocol processing unit, complete security and certainty higher, delay smaller data communication network standards, improved fault tolerance and integrity of communication systems. The design is completed the bus control nodes to achieve specific functions, bus control node as the root exchanges information with a remote node, received remote nodes’ status information to achieve remote monitoring and ensure proper operation of the entire system. Use Veriolg complete logic design hardware description language, all function module partition method to complete the process of utilizing design, completion of the 1394 bus control node communication mechanism correct target. Include initialization process design, design work status, STOF message synchronization mechanism, communication flow between the node and the link layer and specific message handling mechanism, improve the design and versatility readable line, improves troubleshooting efficiency so that more targeted trouble spots. In the process of hardware design, using Flash to restore the configuration information of the receiving and sending messages, this design has shortened the communication delay time. Use UVM verification methodology to establish a verification platform, complete software development, including PCI components, LLC components, scoreboard components and reference models, and run them in Linux operating system. UVM verification platform is highly automated, which provides chip development cycle, reduces development costs and achieves a large-scale randomized validation, successfully completed a functional simulation of the design work.The design of the research work validates superiority of the IEEE1394 bus AS5643 protocol in the field of avionics, also explores its future use in a variety of aerospace equipment.